Defines a test description language that: Facilitates the transfer of large volumes of digital test vector data from CAE environments to automated test equipment ATE environments, Specifies pattern, format, and timing information sufficient to define the application of digital test vectors to a device under test (DUT), Supports the volume of test vector data generated from structured tests such as scan/automatic test pattern generation (ATPG), integral test techniques such as built-in self test (BIST), and functional test specifications for IC designs and their assemblies, in a format optimized for application in ATE environments.